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NCV7513B
Table 4. Refresh and Reference Register
A 2
0
A 1
1
A 0
0
D 5
R 5
D 4
R 4
D 3
R 3
D 2
R 2
D 1
R 1
D 0
R 0
CHANNELS 5 ? 3
CHANNELS 2 ? 0
25% V FLTREF
50% V FLTREF
75% V FLTREF
V FLTREF
t FR = 10 ms
t FR = 40 ms
t FR = 10 ms
t FR = 40 ms
X
X
X
X
X
X
0
1
0
0
1
1
X
X
X
X
0
1
0
1
X
X
X
X
X
X
X
X
0
1
X
X
0
0
1
1
X
X
X
X
0
1
0
1
X
X
X
X
Flag Mask – Register 3
The drain feedback from each channel’s DRN X input is
combined with the channel’s K X mask bit (Table 5). When
K X = 1, a channel’s mask is cleared and its feedback to the
FLTB and STAB flags is enabled. At powerup, each bit is
set to 0 (all masks set).
Table 5. Flag Mask Register
A 2 A 1 A 0 D 5 D 4 D 3 D 2 D 1 D 0
0 1 1 K 5 K 4 K 3 K 2 K 1 K 0
0 = MASK SET
1 = MASK CLEAR
The STAB flag is influenced when a mask bit changes
CLR → SET after one valid SPI frame. FLTB is influenced
after two valid SPI frames. This is correct behavior for
FLTB since, while a fault persists, the FLTB will be set
when CSB goes LO → HI at the end of an SPI frame. The
mask instruction is decoded after CSB goes LO → HI so
FLTB will only reflect the mask bit change after the next
SPI frame. Both FLTB and STAB require only one valid
SPI frame when a mask bit changes SET → CLR.
Null Register – Register 4
Fault information is always returned when any register
is addressed. The null register (Table 6) provides a way to
read back fault information without regard to the content
of D X .
Table 6. Null Register
A 2 A 1 A 0 D 5 D 4 D 3 D 2 D 1 D 0
1 X X X X X X X X
Gate Driver Control and Enable
Each GAT X output may be turned on by either its
respective parallel IN X input or the internal G X (Gate
Select) register bit via SPI communication. The device’s
common ENA X enable inputs can be used to implement
global control functions, such as system reset, overvoltage
or input override by a watchdog controller. Each parallel
input and the ENA2 input have individual internal
pulldown current sources. The ENA1 input has an internal
pulldown resistor. Unused parallel inputs should be
connected to GND and unused enable inputs should be
connected to V CC1 . Parallel input is recommended when
low frequency ( v 2.0 kHz) PWM operation of the outputs
is desired.
ENA2 disables all GAT X outputs when brought low.
When ENA1 is brought low, all GAT X outputs, the timer
clock, and the flags are disabled. The fault and gate
registers are cleared and the flags are reset. New serial G X
data is ignored while ENA1 is low but other registers can
be programmed.
When both the ENA1 and ENA2 inputs are high, the
outputs will reflect the current parallel or serial input states.
This allows ENA1 to be used to perform a soft reset and
ENA2 to be used to disable the GAT X outputs during
initialization of the NCV7513B.
The IN X input state and the G X register bit data are
logically combined with the internal (active low)
power ? on reset signal (POR), the ENA X input states, and
the shorted load state (SHRT X ) to control the
corresponding GAT X output such that:
GATX + POR · ENA1 · ENA2 · SHRTx · (INx ) Gx)
(eq. 1)
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